1. Field of the Invention
This invention relates to electronic circuits and, more particularly, to low voltage, high gain current/voltage sense amplifier circuits with improved read access time.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many modern semiconductor memories employ differential bit lines and some sort of differential amplifier or sensing circuit in their design. These differential amplifiers and sense circuits are commonly known as sense amplifiers (or “sense amps”). In addition to memory devices, sense amplifiers may be used in programmable arrays and many other applications. A wide variety of sense amps are known in the art, including current sensing and voltage sensing variations.
For example, dynamic random access memory (DRAM) devices often employ voltage sense amplifiers (VSAs) for detecting the state of a DRAM memory cell. In voltage sensing, the bitline is precharged before the memory cell is activated. When the memory cell is activated, the memory cell charges or discharges the bitline to maintain or change the voltage of the bitline. However, the bitline may be quite long in some memory devices (e.g., in large memory arrays), resulting in a large capacitive load for the memory cell. In some cases, the memory cell may not be able to provide enough cell current to quickly charge or discharge a large bitline, and an excessive amount of time (i.e., read access time) may be needed to read the memory cells. For this reason, voltage sensing may not be preferred in all memory devices.
Current sense amplifiers (ISAs) are also commonly used for detecting the state of a memory cell. For example, current sense amplifiers are well suited for measuring signals on heavily loaded capacitive lines, such as those found in large memory devices or programmable array devices, where it would be slow to measure voltage. Located in a sense amplifier circuit (SA), the current sense amplifier measures a current and turns this into a small differential voltage output. In some cases, the output of a current sense amplifier (ISA) may be passed to a voltage sense amplifier (VSA), which is also located in the sense amplifier circuit for amplifying the low voltage signal into a higher voltage signal. The output of the voltage sense amplifier may then be passed as the output of the sense amplifier circuit.
FIG. 1 illustrates one embodiment of a sense amplifier circuit that may be used for detecting a current (or voltage) differential between complementary bitlines of a memory array (such as memory array 100). In the embodiment shown, current sense amplifier (ISA) 130 is coupled for receiving a pair of differential currents (IBL, IBLB) from one or more complementary bitlines (BL, BLB) of memory array 100. In some cases, ISA 130 may be coupled for receiving the pair of differential currents from only one column of memory cells (e.g., column 0 via COLMUX 110). In other cases, ISA 130 may be coupled for receiving the pair of differential currents from more than one column of memory cells (e.g., columns 0-N via COLMUX 110 to 120). The column multiplexers (COLMUX) are generally used to switch between the pairs of bitlines, depending on the particular column of memory cells selected.
Although not illustrated herein, a voltage sense amplifier (VSA) may also be used for receiving a pair of differential voltages—instead of currents—from the complementary bitlines (BL, BLB) of memory array 100. As noted above, the choice between ISAs and VSAs may depend on several factors including, but not limited to, speed, memory array architecture and technology constraints (e.g., threshold voltages, saturation currents, etc.).
In many cases, ISA 130 may be implemented in three-stages, as shown in FIG. 1. For example, ISA 130 may include a sensing stage (140) for reading the memory cell data by sensing a current (or voltage) differential between a pair of complementary bitlines (BL, BLB), an amplifying stage (150) for amplifying the small differential output signal generated by the sensing stage, and an optional buffering stage (160). If included, the optional buffering stage may be used for supplying the sense amp output signal (SAOUT) with full rails (i.e., for outputting the sense amp signal with a voltage swing that extends between a power supply voltage and a ground supply voltage).
Unfortunately, many conventional sense amp designs fail to meet important design specifications as technological trends progress toward higher speeds, smaller geometries and lower power supply voltages. For example, conventional sense amp designs often fail to meet the fast read access times (e.g., about 4 ns to about 6 ns) specified for high-speed, low voltage (e.g., about 1 volt) memory devices, such as high density Asynchronous SRAM's (among others). In addition, many conventional sense amp designs fail to operate (i.e., fail to sense the correct data) under moderate to extreme mismatch conditions. These mismatch conditions (and therefore, the ability for conventional designs to operate) only worsen as circuit geometries continue to scale to smaller and smaller sizes.
Therefore, a need exists for an improved sense amp design with improved read access times and reduced sensitivities to device mismatch. Such an improved sense amp design would be particularly useful in high-speed, low voltage memory applications.